Technical Field
The present document relates to DC-to-DC converters. In particular, the present document relates to a current sink stage for low drop-out (LDO) regulators.
Background
LDOs are traditionally unidirectional power supplies i.e. they can either sink or source current.
In case of an LDO sourcing current there is either no sink capability or very small current sink capability, which would be triggered only if the voltage at output overshoots a certain percentage more than the expected regulated voltage. The voltage at the output of LDO can overshoot in an event of sudden removal of load.
If the voltage at output overshoots but is within the specified tolerance the current sink would usually not be enabled. This results in skewing of the potential at internal nodes of the LDO and slower response to a load transient (sudden requirement of current by the load), a slower response translating to a larger dip in the regulated output voltage, which may generate a brown-out condition for the chip being powered by LDO, this is especially true for ICs requiring low voltages
A common way to reduce the dip in the output voltage is to increase the output decoupling capacitor which means a larger footprint on the very expensive PCB real estate especially in the case of handheld devices.
Current sinks are also needed to avoid back powering of the battery if current is pushed into the output of LDO by some source external to a PMIC.
Using bi-directional push-pull LDOs may be a solution but they are very complex to compensate and require additional quiescent current. The additional current eats into a very tight power budget for a PMIC in low power mode.
A current sink is implemented using either a comparator or an amplifier. Both have advantages and disadvantages. An amplifier would regulate the voltage at the output by regulating the current it sinks depending on the current sourced into the output of LDO, but are difficult to compensate. Comparators on the other hand don't require any compensation but may suffer from chattering and they don't regulate the output voltage if current pushed into the LDO output is less than the current sink capability of the comparator.
FIG. 1 prior art shows a simplified schematic of an implementation of an LDO with a current sink or over-voltage sink.
P1 is the pass device and A1 is an amplifier controlling the gate of P1. R2, R1 & Rprot form a feedback resistor divider network for regulating the output voltage. C1 is an external decoupling capacitor. The load is an external IC powered by the LDO
A2 and transistor N1 form an over-voltage sink. A2 can be configured as a comparator or as an amplifier. Under normal operation Vov is lower than the reference voltage Vref and the gate of N1 is pulled to ground, so no current is sunk from the output. In an overvoltage condition, if the voltage at Vov is higher than or equal to Vref, the current sink is activated. The gate of N1 is driven by A2 to sink the current from output voltage VOUT.
If A2 is configured as a comparator, the gate of N1 is driven either to supply or ground. If A2 along with N1 and capacitor C1 is configured as an amplifier, the gate of N1 is regulated depending on the difference between Vov and Vref
FIG. 2 prior art shows a plot of a response of the LDO of FIG. 1, wherein A2 is configured as a comparator and a current of 1 mA is sourced into the output of the LDO. As the current sourced is lower than the sink capability of comparator we observe a 20 mV of saw tooth at the output of LDO. The gate of N1 swings between ground and supply voltage. If such an LDO has to power a sensitive analog chip, such a saw tooth response at the output is undesirable. The output voltage, when the sourced current is removed, raises nearly 35 mV above the regulated target voltage and all the internal nodes of LDO are completely skewed at this point.
FIG. 3 prior art shows a plot of a response of the LDO of FIG. 1, wherein A2 is configured as an amplifier and a current of 1 mA is sourced into the output of the LDO. As FIG. 3 shows, the output voltage of the LDO is regulated and the gate of N1 is regulated to sink 1 mA of current. The output voltage, when the sourced current is removed, is nearly 10 mV higher than the regulated target voltage and all the internal nodes of LDO are completely skewed at this point.
It is a challenge for designers of LDOs to achieve LDOs, wherein activation of current sink is independent of the percentage overshoot above the regulated output voltage, that regulate the output voltage to a defined output voltage if the current sourced into LDO is less than the current sink capability, wherein a dip in the output voltage is within a minimal load transient specification, any possibility of brown-out condition is avoided, and which don't require larger capacitors at the output to avoid a possibility of brown-out condition.
Solutions are desired to avoid the drawbacks mentioned above.